Concurrent processing of multiple data channels in analog or mixed-signal systems may lead to crosstalk among channels and/or pattern noise within different channels. For example, while the capture of the analog data from a sensor array may be carried out in parallel, the processing of the captured data may include both serial and parallel processing. This mixed data processing often may cause the undesired crosstalk/pattern noise.
By way of example, FIG. 1(A) shows a system-on-chip (SOC) architecture of an analog-to-digital converter (ADC) system coupled at inputs with an array of analog sensors and at outputs with a field-programmable gate array (FPGA). In this example, the array of analog sensors may include 256 sensors such as photo diodes. The analog sensors may convert physical quantities (such as light intensity) into analog electrical signals. The ADC system may include internal sampling circuits 0-255 (integrators and correlated-differential sampling devices (CDSs)), multiplexers, and analog-to-digital converters (ADCs). The analog signals on the large analog sensor may be captured simultaneously. In practice, a large analog sensor may be divided into groups of sensors to be handled by an array of SOC cells (or sub-systems) like the one shown in FIG. 1(B). For example, the 256 analog sensors may be divided into 8 groups, each group having 32 analog sensors. Thus, each SOC cell (or sub-system) may process the 32 analog inputs sequentially based on a common clock signal between cells.
Referring to FIG. 1(B), internal sampling circuits that are coupled to analog sensors may, acting as analog receivers, capture and store the analog signals. An analog-to-digital converter (ADC) may be coupled to the internal sampling circuits via a multiplexer. The multiplexer may have multiple input nodes (e.g., 32 input nodes), one output node, and a select node. Thus, the multiplexer may connect one of the input nodes to the output node based on an index signal on the select node. For example, each input node may be labeled with an index number. Thus, when an index number is supplied to the select node of the multiplexer, the input node correspondingly labeled with the index number may be connected to the output by forming a signal path from the selected input node to the output node. The ADC may retrieve an analog signal through the selected signal path. The ADC may then convert the analog signal through the selected signal path into a digital signal. Commonly, a counter, coupled to the select node, may provide sequentially-increasing count number to the select node. The sequentially-increasing count number may represent the index number of input nodes to be connected to the output node. For this example, the counter coupled to the multiplexer may generate indices of 0 to 31 sequentially in accordance with a clock signal CLK_ADC. The input nodes may be connected to the output node in the order of 0-31. After cycling through the 32 input nodes, the counter may automatically reset to 0 before the start of next acquisition cycle of 32 analog signals to the ADC sub-system.
Referring to FIG. 1(B), for each acquisition cycle of the ADC sub-system, the 32 analog channels of sensor data may be sampled in parallel and then processed sequentially through the ADC converter. In this design, the analog signals may be sampled in parallel onto internal sampling capacitors. While retrieving analog signals stored in the capacitors via multiplexers, crosstalk may result among signal paths of different data channels in multiplexers. FIG. 2 illustrates a common layout of routings where parasitic capacitance (CP) may exist between routings of the two 4:1 and one 8:1 sub-multiplexers. These parasitic CP's may produce undesired crosstalk. Although crosstalk among different routes may be minimized by optimizing system timing and the chip layout, there still may be some level of residual crosstalk that may create adverse effects perceivable to an observer.
Besides crosstalk, pattern noise may be another source of undesired effects that may arise in designs like FIG. 1. Still, by way of the example shown in FIG. 1(B), for the 32 analog sensors, the ADC may sequentially convert the analog signals stored in the internal sampling capacitors. Therefore, the throughput of the system may be 32*TADC, where TADC is the ADC conversion rate (or the ADC sampling frequency—the speed at which the ADC converter outputs a new binary number).
FIG. 3 shows a portion of an acquisition cycle (eight out of 32 ADC cycles). In addition to the ADC clock, the cell also may run other clock and timing signals including a reset time signal (Reset) for resetting the system, and two clocks for the CDS operation (CLK_CDS1, CLK_CDS2). These additional timing signals and clocks may generate system activities. Over the entire acquisition cycle (of 32 ADC cycles), there may be different levels of system activities on and off the ADC chip. These activities may cause adverse effects on the conversion results. Referring to FIG. 3, the ADC conversion may be exposed to the system activities caused by system resetting during pulse 1 (and similarly, pulse 1 in the next acquisition cycle) and disturbed by the parallel sampling clock signals (CLK_CDS1, CLK_CDS2) during pulses 4 and 6 (and similarly, pulses 4 and 6 in the next ADC cycle). The system may be quiet during pulses 2, 3, 5, 7, and 8 of ADC conversion. When these system activities repeatedly happen at fixed time instances during each ADC acquisition period, they may cause fixed pattern noise in the eventual digital signals.
On an array image sensor (such as an x-ray image sensor), crosstalk/pattern noise may be easily perceived by a human observer even when the amount of crosstalk/pattern noise is much less than the overall system noise. Therefore, even a small amount of crosstalk/pattern noise may adversely affect the overall performance of the ADC system. Therefore, there is a need to reduce the adverse effects of correlated noise caused by the fixed relationship between sensors and system activities.